The present disclosure relates to semiconductor devices, and specifically relates to insulated gate bipolar transistors (IGBTs) and horizontal MOS transistors.
In recent years, associated with a significant decline in prices of color plasma display panels (PDPs), there is a huge demand for a reduction in cost of semiconductor devices used therein. In many cases, in a scan driver IC of the color PDP, a silicon integrated circuit having a horizontal IGBT and a control circuit with a low breakdown voltage which are provided as one chip on an SOI substrate, is employed as an output drive device.
In order to reduce cost of the scan driver IC, reducing the size of the horizontal IGBT, which occupies a large area in a chip, is very effective, but to do so, it is necessary to improve the current capability of the horizontal IGBT.
The current capability of the horizontal IGBT needs to be examined mainly from two viewpoints, that is, performance characteristics such as an on-state voltage and a saturation current, and element breakdown such as on breakdown voltage or the safe operating area (SOA) and the electro-static discharge (ESD). Since the present disclosure is effective not only for the IGBTs but also for the MOS transistors, the term “saturation current” used herein refers to a saturation current similar to a saturation current in the MOS transistors, that is, a collector current in an area exhibiting a tendency to saturate. The on breakdown voltage is a collector voltage which breaks down in the on state. The SOA refers to the on breakdown voltage and operable current-voltage ranges which can be defined by a breakdown current of the on breakdown voltage. Thus, the on breakdown voltage and the SOA can be considered as having a similar meaning in the present disclosure. Further, regarding the saturation current, the on breakdown voltage, and the SOA, both of a direct current (DC) input and a pulse input need to be considered.
In the present disclosure, the inventors measured the on breakdown voltage of an IGBT by applying a pulse signal with a width of 100 ns to a collector, using a transmission line pulse (TLP) measurement device. On the other hand, the saturation current is measured by an input of a DC signal.
The on breakdown voltage is lowered as the saturation current increases. Thus, in general, there is a trade-off relationship between the on breakdown voltage and the saturation current.
The saturation current relies on the resistance component mainly at a time when the device is in the on state. A channel resistance that occurs in a region under a gate insulating film is one of main resistance components. It is thus important to reduce the channel resistance. Further, in order to increase the on breakdown voltage, it is important to reduce latch-up. An equivalent circuit of the horizontal IGBT has a thyristor structure as shown in FIG. 16. Once the thyristor operates and latch-up occurs, the latch-up cannot be controlled by a gate voltage. This leads to a low impedance state, and heat causes breakdown. One of conditions of occurrence of the latch-up is α(NPN)+α(PNP)≧1 where α(NPN) and α(PNP) are a common-base current gain of a parasitic NPN transistor and a common-base current gain of a parasitic PNP transistor, respectively. This means that it is important to reduce the current gain α of each of the bipolar transistors in order to reduce the occurrence of the latch-up.
Since the performance characteristics of the PNP transistor retate to the saturation current, if the current gain α is reduced too much, the superiority of the PNP transistor over the MOS transistor will be reduced. Thus, to avoid latch-up, the focus is placed on controlling a turn-on operation (hereinafter referred to as “on operation”) of the parasitic NPN transistor. In particular, to control the on operation of the parasitic NPN transistor, it is effective to reduce a body resistance Rb of a lower portion of an emitter region. If a collector current increases when the horizontal IGBT is in the on state, the voltage drops significantly in a P type body region at a parasitic resistance Rb. If this voltage drop becomes equal to or exceeds a built-in potential Vbi, the on operation starts. For this reason, reducing the parasitic resistance Rb is particularly important.
As a conventional structure that can improve the trade-off relationship, a device structure in which a body region has a retrograde profile has been suggested as disclosed in Japanese Unexamined Patent Publication No. 2008-147415 (Patent Document 1).
In the retrograde profile, the impurity concentration is increased from a surface (hereinafter also referred to as a Si surface) of a silicon (Si) layer in a depth direction, and the impurity concentration peaks at a lower portion of the emitter region. It is therefore possible to reduce the parasitic resistance Rb while reducing an increase in a channel resistance.
FIG. 17 shows a schematic cross section of an element structure of the horizontal IGBT disclosed in Patent Document 1. As shown in FIG. 17, a P type first body region 4, a P− type second body region 5, an N− type drift region 6, and an N type buffer region 7 are formed in an upper portion of an SOI substrate formed by adhering a supporting substrate 1, a buried insulating film 2, and a low concentration P type semiconductor layer 3. A high concentration N+ type first emitter region 8 and an N type second emitter region 9 of which the concentration is lower and the diffusion depth is deeper than the concentration and the diffusion depth of the first emitter region 8 are formed in an upper portion of the first body region 4. In general, the first emitter region 8 and the second emitter region 9 also serve as an N type source region and an N type drain region of a low breakdown voltage N channel MOS in a logic element integrated in the same chip. In general, the N type source region and the N type drain region are formed by two types of diffusion layers including a high concentration N type region for ohmic contact and a low concentration N type region called lightly-doped-drain (LDD). The diffusion depth of the second emitter region 9 corresponding to the low concentration diffusion layer (LDD) is deeper, in general, than the diffusion depth of the first emitter region 8 corresponding to the high concentration diffusion layer.
A P+ type collector region 10 formed on the surface of the N type buffer region 7 and a P+ type body contact diffusion region 11 formed on the surface of the first body region 4 are made of the same high concentration diffusion layer. A gate electrode 13 extends from above a gate insulating film 12 to above a field oxide film 15. A sidewall spacer 14 is provided on a sidewall of the gate electrode 13. An emitter electrode 16 is formed on the first emitter region 8 and the body contact diffusion region 11. A collector electrode 17 is formed on the collector region 10.
The first body region 4 has a vertical concentration distribution in which the P type impurity concentration increases from the surface of the P type semiconductor layer 3 and peaks at a lower portion of the emitter region 8, and extends in a lateral direction to diffuse into part of the region under the emitter region 8. The lateral length of the impurity diffusion from the highest impurity concentration portion under the end of the gate electrode 13 closer to the emitter region 8 to a region under the gate electrode 13 is equivalent to or longer than the vertical length of the impurity diffusion from the highest impurity concentration portion toward the supporting substrate.
Here, in the first body region 4 whose impurity concentration increases from the Si surface in the depth direction and which includes the highest impurity concentration portion under the emitter region 8 (this is called a retrograde profile and a characteristic of the Patent Document 1), the parasitic resistance of the first body region 4 under the emitter region 8 can be reduced, and therefore, the first body region 4 has an effect on the control of the operation of the parasitic bipolar transistor. Further, the first body region 4 extends from under the end of the gate electrode 13 closer to the emitter region 8 to a region under the gate electrode 13, that is, toward the collector region 10. This configuration can reduce the current gain of the parasitic bipolar transistor in the lateral direction, and therefore has an effect on the control of the operation of the parasitic bipolar transistor. As a result, a breakdown current at which the parasitic bipolar transistor operates can be increased, and the on breakdown voltage can be increased. Further, since the first body region 4 has a retrograde profile, even if the first body region 4 is made to have a high impurity concentration at its deep portion, it is possible to reduce effects on an increase in impurity concentration of the Si surface. As a result, the saturation current can be increased without an increase in a channel resistance, and it is possible to improve the trade-off relationship between the on breakdown voltage and the saturation current.
Next, a method for manufacturing a conventional structure shown in Patent Document 1 will be described using a schematic flow diagram of cross sections of FIG. 18A to FIG. 18F.
First, as shown in FIG. 18A, a supporting substrate 1, a buried oxide film 2 with a thickness of 2.0 μm, and a p-type semiconductor layer 3 with a thickness of 3.5 μm are adhered together to form an SOI substrate, on which a commonly-used diffusion technique, such as ion implantation, photolithography and a drive-in technique (a heat treatment), is repeatedly performed to sequentially form a second body region 5, an N type buffer region 7, and an N− type drift region 6 in the p-type semiconductor layer 3.
Next, as shown in FIG. 18B, a field oxide film 15 with a thickness of 540 nm is formed in an upper portion of the N− type drift region 6 so as to overlap with part of the N type buffer region 7. After that, boron (B) ions are implanted in an upper portion of the second body region 5 at acceleration energy of 180 keV and a dose amount of from about 5E+13 ions/cm2 to about 9E+13 ions/cm2, thereby forming a first body region 4.
Next, as shown in FIG. 18C, a gate insulating film 12 is formed on a region extending from an end portion of the first body region 4 closer to the field oxide film 15 to the field oxide film 15. After that, a gate electrode 13 made of an N type polysilicon film doped with phosphorus (P) at a high concentration is formed on the gate insulating film 12.
Next, as shown in FIG. 18D, phosphorus (P) ions are implanted in an upper portion of the first body region 4 at acceleration energy of 70 keV and a dose amount of about 4E+13 ions/cm2, thereby forming an N type second emitter region 9. Since the gate electrode 13 and the second emitter region 9 are formed in a self-aligned manner, the second emitter region 9 only slightly enters in a region under the gate electrode 13, and the end portion of the second emitter region 9 closer to the gate electrode 13 almost coincides with the end portion of the gate electrode 13 closer to the second emitter region 9.
Next, as shown in FIG. 18E, a sidewall spacer 14 is formed on a side surface of the gate electrode 13, using a CVD insulating film. After that, arsenic (As) ions are implanted in the second emitter region 9, thereby forming a high concentration N+ type first emitter region 8.
Next, as shown in FIG. 18F, a p+ type body contact region 11 and a p+ type collector region 10 are simultaneously formed by BF2 ion implantation. After that, although not shown, an insulating film is formed on the entire surface, and contact holes are selectively formed in part of the insulating film. Then, a multilayer structure comprised of a metal interconnect that includes an emitter electrode and a collector electrode, and of the insulating film is formed. Further, an insulating film for protection is formed to cover the surface.
The trade-off relationship between the on breakdown voltage and the saturation current can be further improved if the device technique disclosed in U.S. Pat. No. 6,700,160 (Patent Document 2) is used. Specifically, in Patent Document 2, N type impurity ions opposite to the conductivity type (P type) of the body region are implanted in a channel surface, thereby reducing a P type impurity concentration near the surface of the body region. The N type impurities are implanted to a diffusion depth that does not affect a deep portion of the body region. Thus, effects on a reduction of the on breakdown voltage can be reduced.
Next, a schematic cross section of an element structure when the structure in Patent Document 2 is applied to the structure in Patent Document 1 is shown in FIG. 19. An N type surface diffusion region 18 is a region added by the combination with Patent Document 2, and that is a difference from the structure in Patent Document 1.
The surface diffusion region 18 is formed in the Si surface from an end portion of the second emitter region 9 to an end portion of the field oxide film 15 closer to the gate electrode 13. Due to the surface diffusion region 18, the P type impurity concentration of the surface of the P type first body region 4 is reduced, and a threshold voltage is reduced. At the same time, the channel length is shortened and the channel resistance is reduced. As a result, the saturation current can be increased.
Since the surface diffusion region 18 is provided so as to slightly overlap the second emitter region 9, the surface diffusion region 18 does not reduce the P type impurity concentration of the first body region 4 located under the first emitter region 8. Further, since the parasitic resistance Rb does not increase, it is possible to reduce an effect on the on operation of the parasitic NPN transistor.